The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a method and structure for integrating metal-insulator-metal (MIM) capacitors within dual damascene processing techniques.
In many mixed signal or high frequency RF applications, both high performance, high-speed capacitors and inductors are utilized. Low series resistance, low loss, high Q and low (RC) time constants are characteristic of such components in high frequency applications for achieving high performance. In addition, these device structures are fabricated by processes compatible with CMOS processing (e.g., using AlCu alloys, pure copper, Ti, TiN, Ta, and TaN, possibly in combination, in both subtractive-etch and dual damascene structures).
In particular, a metal-insulator-metal (MIM) capacitor is commonly used in high performance applications in CMOS technology. Typically, the MIM capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from metal films including, but limited to, Al, AlCu alloys, Ti, TiN, Ta, and TaN that are patterned and etched through the use of several photolithography photomasking steps. The thin insulating dielectric layer is typically made from silicon oxide or silicon nitride, deposited by chemical vapor deposition (CVD), for example.
Because conventional MIM capacitors utilize metal plates as upper electrodes, additional process steps beyond existing dual damascene methods are needed to fabricate the plates. In addition, the total thickness associated with the upper electrode and the MIM dielectric is approaching that of a dual damascene layer, thus making integration more difficult because of the resulting induced topography. Accordingly, it would be desirable to be able to produce MIM capacitors in a manner that results in as little additional processing as possible and that has a minimal effect on device topography.